HD6417034 Datasheet, PDF (350/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

11.2.2 Port B Data Register (PBDR)
The port B data register (PBDR) is a 16-bit read/write register that stores output data for groups 0–
3 when TPC output is used. For details of PBDR, see section 16, I/O Ports.
Bit: 15
14
13
12
11
10
9
8
Bit name: PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR PB8DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Bits set to TPC output by NDERA or NDERB are read-only.
Bit: 7
6
5
4
3
2
1
0
Bit name: PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Bits set to TPC output by NDERA or NDERB are read-only.
11.2.3 Next Data Register A (NDRA)
NDRA is an eight-bit read/write register that stores the next output data for TPC output groups 1
and 0 (TP7–TP0). When used for TPC output, the contents of NDRA are transferred to the
corresponding PBDR bits when the ITU compare match specified in the TPC output control
register, TPCR, occurs.
The address of NDRA differs depending on whether TPCR settings select the same trigger or
different triggers for TPC output groups 1 and 0. NDRA is initialized to H'00 by a reset. It is not
initialized in standby mode.
Same Trigger for TPC Output Groups 1 and 0: If TPC output groups 1 and 0 are triggered by
the same compare match, the address of NDRA is H'FFFFF5. The upper 4 bits become group 1
and the lower 4 bits become group 0. Address H'5FFFFF7 in such cases consists entirely of
reserved bits. These bits cannot be modified and are always read as 1.
Address H'5FFFFF5:
• Bits 7–4 (Next Data 7–4 (NDR7–NDR4)): NDR7–NDR4 store the next output data for TPC
output group 1.
• Bits 3–0 (Next Data 3–0 (NDR3–NDR0)): NDR3–NDR0 store the next output data for TPC
output group 0.
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