HD6417034 Datasheet, PDF (156/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

8.2.8 Refresh Timer Counter (RTCNT)
The refresh timer counter (RTCNT) is a 16-bit read/write register that is used as an 8-bit upcounter
that generates refresh or interrupt requests. When the input clock is selected by clock select bits 2–
0 (CKS2–CKS0) in RTCSR, that clock makes the RTCNT start incrementing. When the values of
RTCNT and the refresh time constant register (RTCOR) match, RTCNT is cleared to H'0000 and
the CMF flag in RTCSR is set to 1. When the RFSHE bit in RCR is also set to 1, a CAS-before-
RAS refresh is performed. When the CMIE bit in RTCSR is also set to 1, a compare match
interrupt (CMI) is generated.
Bits 15–8 are reserved and are not incremented. These bits are always read as 0.
RTCNT is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode.
To prevent RTCSR from being written incorrectly, it must be written by a different method from
most other registers. A word transfer operation is used, H'69 is written in the upper byte, and the
actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access.
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
Bit: 7
6
5
4
3
2
1
0
Bit name:
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
8.2.9 Refresh Time Constant Register (RTCOR)
The refresh time constant register (RTCOR) is a 16-bit read/write register that sets the compare
match cycle used with RTCNT. The values in RTCOR and RTCNT are constantly compared.
When they match, the compare match flag (CMF) is set in RTCNT and RTCSR is cleared to
H'0000. If the RFSHE bit in RCR is set to 1 when this happens, a CAS-before-RAS (CBR) refresh
is performed. When the CMIE bit in RTCSR is also set to 1, a compare match interrupt (CMI) is
generated.
Bits 15–8 are reserved and cannot be used to set the cycle. These bits are always read as 0.
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