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HD6417034 Datasheet, PDF (182/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034 | |||
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Tp
CK
Tr
Tc1
Tc2
A21âA0
RAS
CAS
Read
WRH, WRL
AD15âAD0
Row address
Column address
Write
WRH, WRL
AD15âAD0
Figure 8.18 Long Pitch Access Timing
8.5.3 Wait State Control
Precharge State Control: When the microprocessor clock frequency is raised and the cycle
period shortened, 1 cycle may not always be sufficient for the precharge time for the RAS signal
when the DRAM is accessed. The BSC allows the precharge cycle to be set to 1 state or 2 states
using the RAS signal precharge cycles bit (TPC) in DCR. When the TPC bit is 0, the precharge
cycle is 1 state; when TPC is 1, the precharge cycle is 2 states. Figure 8.19 shows the timing when
the precharge cycle is 2 states.
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