HD6417034 Datasheet, PDF (644/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table A.42 Bit Functions (cont)
Description
Bit Bit Name
DRAM Space
Value (BCRDRAME = 1)
Area 1 External Memory Space
(BCRDRAME = 1)
1 Write wait 0
state control
(WW1)
1
Column address cycle: 1 cycle
(short-pitch)
Setting prohibited
Column address cycle: Wait state Wait state is 2 cycles + WAIT
is 2 cycles + WAIT (long-pitch)
(Initial value)
Note: * During a CBR refresh, the WAIT signal is ignored and the wait state inserted using the
RLW1 and RLW0 bits.
A.2.42 Wait State Control Register 2 (WCR2)
BSC
• Start Address: H'5FFFFA4
• Bus Width: 8/16/32
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
15
DRW7
1
R/W
14
DRW6
1
R/W
13
DRW5
1
R/W
12
DRW4
1
R/W
11
DRW3
1
R/W
10
DRW2
1
R/W
9
DRW1
1
R/W
8
DRW0
1
R/W
Bit:
Bit name:
Initial value:
R/W:
7
DWW7
1
R/W
6
DWW6
1
R/W
5
DWW5
1
R/W
4
DWW4
1
R/W
3
DWW3
1
R/W
2
DWW2
1
R/W
1
DWW1
1
R/W
0
DWW0
1
R/W
608