HD6417034 Datasheet, PDF (34/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

A.2.38 Break Address Mask Register L (BAMRL) UBC................................................ 604
A.2.39 Break Bus Cycle Register (BBR) UBC................................................................ 605
A.2.40 Bus Control Register (BCR) BSC........................................................................ 606
A.2.41 Wait State Control Register 1 (WCR1) BSC ....................................................... 607
A.2.42 Wait State Control Register 2 (WCR2) BSC ....................................................... 608
A.2.43 Wait State Control Register 3 (WCR3) BSC ....................................................... 610
A.2.44 DRAM Area Control Register (DCR) BSC ......................................................... 611
A.2.45 Parity Control Register (PCR) BSC ..................................................................... 613
A.2.46 Refresh Control Register (RCR) BSC.................................................................. 614
A.2.47 Refresh Timer Control/Status Register (RTCSR) BSC........................................ 615
A.2.48 Refresh Timer Counter (RTCNT) BSC................................................................ 616
A.2.49 Refresh Timer Constant Register (RTCOR) BSC................................................ 617
A.2.50 Timer Control/Status Register (TCSR) WDT ...................................................... 617
A.2.51 Timer Counter (TCNT) WDT .............................................................................. 619
A.2.52 Reset Control/Status Register (RSTCSR) WDT .................................................. 619
A.2.53 Standby Control Register (SBYCR) Power-Down State ..................................... 620
A.2.54 Port A Data Register (PADR) Port A................................................................... 621
A.2.55 Port B Data Register (PBDR) Port B ................................................................... 622
A.2.56 Port C Data Register (PCDR) Port C ................................................................... 623
A.2.57 Port A I/O Register (PAIOR) PFC ....................................................................... 624
A.2.58 Port B I/O Register (PBIOR) PFC........................................................................ 625
A.2.59 Port A Control Register 1 (PACR1) PFC............................................................. 626
A.2.60 Port A Control Register 2 (PACR2) PFC............................................................. 628
A.2.61 Port B Control Register 1 (PBCR1) PFC ............................................................. 630
A.2.62 Port B Control Register 2 (PBCR2) PFC ............................................................. 632
A.2.63 Column Address Strobe Pin Control Register (CASCR) PFC............................. 634
A.2.64 TPC Output Mode Register (TPMR) TPC ........................................................... 635
A.2.65 TPC Output Control Register (TPCR) TPC ......................................................... 636
A.2.66 Next Data Enable Register A (NDERA) TPC...................................................... 638
A.2.67 Next Data Enable Register B (NDERB) TPC ...................................................... 638
A.2.68 Next Data Register A (NDRA) TPC
(When the Output Triggers of TPC Output Groups 0 and 1 are the Same) ......... 639
A.2.69 Next Data Register A (NDRA) TPC
(When the Output Triggers of TPC Output Groups 0 and 1 are the Same) ......... 639
A.2.70 Next Data Register A (NDRA) TPC
(When the Output Triggers of TPC Output Groups 0 and 1 are Different) ......... 640
A.2.71 Next Data Register A (NDRA) TPC
(When the Output Triggers of TPC Output Groups 0 and 1 are Different) ......... 640
A.2.72 Next Data Register B (NDRB) TPC
(When the Output Triggers of TPC Output Groups 2 and 3 are the Same) ......... 641
A.2.73 Next Data Register B (NDRB) TPC
(When the Output Triggers of TPC Output Groups 2 and 3 are the Same) ......... 641
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