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HD6417034 Datasheet, PDF (88/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034 | |||
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Exception
source
Reset
Address
error
Interrupt
Instruction
⢠Power-on reset
⢠Manual reset
⢠CPU address error
⢠DMA address error
⢠NMI
⢠User break
⢠IRQ
⢠On-chip module
⢠Trap instruction
⢠General illegal
instruction
⢠Illegal slot
instruction
Priority
High
⢠IRQ0âIRQ7
⢠Direct memory access
controller
⢠16-bit integrated timer
pulse unit
⢠Serial communication
interface
⢠Parity control unit
(part of the bus con-
troller)
⢠A/D converter
⢠Watchdog timer
⢠DRAM refresh control
unit (part of the bus
controller)
⢠TRAPA instruction
⢠Undefined code
⢠Undefined instruction
or instruction that
rewrites the PC*1
placed directly after Low
a delayed branch
instruction*2
Notes: *1 The instructions that rewrite the PC are JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, and
TRAPA.
*2 The delayed branch instructions are JMP, JSR. BRA. BSR, RTS, and RTE.
Figure 4.1 Exception Source Types and Priority
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