HD6417034 Datasheet, PDF (635/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

A.2.33 Interrupt Priority Setting Register E (IPRE)
INTC
• Start Address: H'5FFFF8C
• Bus Width: 8/16/32
Register Overview:
Bit: 15
14
13
12
11
10
9
8
Bit name:
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name:
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W
—
—
—
—
Table A.34 IPRE Bit Functions
Bit
Bit name
Description
15–12 (Set SCI1 priority level)
Sets the SC1 priority level value
11–8 (Set PRT*¹ and A/D priority levels) Sets the PRT*¹ and A/D priority level values
7–4
(Set WDT and REF*² priority
levels)
Sets the WDT and REF*² priority level value
Notes
*1 PRT: Parity control section within the bus state controller. See section 8, Bus State
Controller (BSC), for more information.
*2 REF: DRAM refresh control section within the bus state controller. See section 8, Bus
State Controller (BSC), for more information.
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