HD6417034 Datasheet, PDF (629/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table A.28 CHCR0–CHCR3 Bit Functions (cont)
Bit Bit name
Value Description
11–8 Resource select bits 1 0 1 1 IMIA3 (input capture A/compare match A interrupt
3–0 (RS3–RS0) (cont)
request of on-chip ITU3)*⁴
1 1 0 0 Auto request (transfer request automatically generated
within DMAC)*⁴
1 1 0 1 ADI (A/D conversion end interrupt request of on-chip
A/D converter)
1 1 1 0 Reserved (cannot be set)
1 1 1 1 Reserved (cannot be set)
7
Acknowledge mode 0
bit (AM)*¹
1
DACK output in read cycle
DACK output in write cycle
(Initial value)
6
Acknowledge level 0
bit (AL)*¹
1
DACK is active-high signal
DACK is active-low signal
(Initial value)
5
DREQ select bit
0
(DS)*¹
1
DREQ detected at low
DREQ detected on falling edge
(Initial value)
4
Transfer bus mode bit 0
(TM)
1
Cycle-steal mode
Burst mode
(Initial value)
3
Transfer size bit (TS) 0
Byte (8 bits)
(Initial value)
1
Word (16 bits)
2
Interrupt enable bit 0
(IE)
1
Interrupt request disabled
Interrupt request enabled
(Initial value)
1
Transfer end flag bit 0
(TE)
DMA transferring or DMA transfer halted (Initial value)
Clear Conditions: TE bit read and then 0 written in TE
1
DMA transfer ends normally
0
DMA enable bit (DE) 0
DMA transfer disabled
(Initial value)
1
DMA transfer enabled
Notes: *1 Only valid in channels 0 and 1.
*2 Transfer to external device from memory mapped external device or external memory
with DACK.
*3 Transfer from external device to memory mapped external device or external memory
with DACK.
*4 Dual address mode.
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