HD6417034 Datasheet, PDF (15/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Section
Page
19.1.2 Register
460
Table 19.2 Standby
Control Register
(SBYCR)
20.1.2 DC
467
Characteristics
Table 20.2 DC
Characteristics
Table 20. 2 DC

Characteristics
Table 20.3
471
Permitted Output
Current Values
20.1.3 AC
472
Characteristics
(1) Clock Timing
Table 20.4 Clock
Timing
(2) Control Signal 474
Timing
Table 20.5 Control
Signal Timing
(3) Bus Timing
478,
Table 20.6 Bus
479
Timing (1)
Description
Edition
Note added
6
Name
Abbreviation R/W Initial Value Address* Access size
Standby control register SBYCR
R/W H'1F
H'5FFFFBC 8, 16, 32
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
16.6 MHz deleted
6
Table of 16.6 MHz deleted
6
16.6 MHz deleted
6
16.6 MHz deleted
6
16.6 MHz deleted
6
Description amended
6
Read data access time 1*⁶
Read data access time 2*⁶
t_ACC1
t_ACC2
t_cyc – 30*⁴
—
t_cyc × (n+2) – —
30*³
ns 20.8, 20.11, 20.12
ns 20.9, 20.10,
20.13–20.15
Table 20.7 Bus
Timing (2)
Table 20.7 Bus
Timing (2)
Read data access time from
CAS 2*⁶
Read data access time from
RAS 1*⁶
Read data access time from
RAS 2*⁶
t_CAC2
t_RAC1
t_RAC2
t_cyc × (n+1) – —
25*³
t_cyc × 1.5 – 20 —
t_cyc × (n+2.5) —
– 20*³
ns 20.13–20.15
ns 20.11, 20.12
ns 20.13–20.15

494
Data setup time for CAS
CAS setup time for RAS
Row address hold time
t_DS
t_CSR
t_RAH
0*⁵ —
10 —
10 —
ns 20.11, 20.13
ns 20.16–20.18
ns 20.11, 20.13
Table deleted
6
Description amended
6
Read data access time 1*⁴ t_ACC1 t_cyc – 44
— ns 20.21, 20.24, 20.25
Read data access time 2*⁴ t_ACC2 t_cyc × (n+2) – 44*² — ns 20.22, 20.23,
20.26–20.28