HD6417034 Datasheet, PDF (394/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Bit 3: MPIE
0
1
Description
Multiprocessor interrupts are disabled (normal receive operation)
(Initial value)
MPE is cleared to 0 when:
1. MPIE is cleared to 0, or
2. Multiprocessor bit (MPB) is set to 1 in receive data.
Multiprocessor interrupts are enabled: Receive-data-full interrupt
requests (RXI), receive-error interrupt requests (ERI), and setting of
the RDRF, FER, and ORER status flags in the serial status register
(SSR) are disabled until the multiprocessor bit is set to 1.
The SCI does not transfer receive data from RSR to RDR, does not
detect receive errors, and does not set the RDRF, FER, and ORER
flags in the serial status register (SSR). When it receives data that
includes MPB = 1, MPB is set to 1, and the SCI automatically clears
MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in
SCR are set to 1), and allows FER and ORER to be set.
• Bit 2 (Transmit-End Interrupt Enable (TEIE)): TEIE enables or disables the transmit-end
interrupt (TEI) requested if TDR does not contain new transmit data when the MSB is
transmitted.
Bit 2: TEIE
0
1
Description
Transmit-end interrupt (TEI) requests are disabled
(Initial value)
The TEI request can be cleared by reading the TDRE bit in the serial
status register (SSR) after it has been set to 1, then clearing TDRE to
0; by clearing the transmit end (TEND) bit to 0; or by clearing the TEIE
bit to 0.
Transmit-end interrupt (TEI) requests are enabled.
• Bits 1 and 0 (Clock Enable 1 and 0 (CKE1 and CKE0)): CKE1 and CKE0 select the SCI clock
source and enable or disable clock output from the SCK pin. Depending on the combination of
CKE1 and CKE0, the SCK pin can be used for general-purpose input/output, serial clock
output, or serial clock input. The SCK pin function should be selected in advance with the pin
function controller (PFC).
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external
clock source is selected (CKE1 = 1). Select the SCI operating mode in the serial mode register
(SMR) before setting CKE1 and CKE0. For further details on selection of the SCI clock
source, see table 13.9 in section 13.3, Operation.
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