HD6417034 Datasheet, PDF (388/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table 13.2 Registers
Channel Address*¹ Name
Abbreviation R/W
Initial Access
Value size
0
H'05FFFEC0 Serial mode register SMR0
R/W H'00 8, 16
H'05FFFEC1 Bit rate register
BRR0
R/W H'FF 8, 16
H'05FFFEC2 Serial control register SCR0
R/W H'00 8, 16
H'05FFFEC3 Transmit data register TDR0
R/W H'FF 8, 16
H'05FFFEC4 Serial status register SSR0
R/(W)*² H'84
8, 16
H'05FFFEC5 Receive data register RDR0
R
H'00 8, 16
1
H'05FFFEC8 Serial mode register SMR1
R/W H'00 8, 16
H'05FFFEC9 Bit rate register
BRR1
R/W H'FF 8, 16
H'05FFFECA Serial control register SCR1
R/W H'00 8, 16
H'05FFFECB Transmit data register TDR1
R/W H'FF 8, 16
H'05FFFECC Serial status register SSR1
R/(W)*² H'84
8, 16
H'05FFFECD Receive data register RDR1
R
H'00 8, 16
Notes: *1 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
*2 Only 0 can be written, to clear flags.
13.2 Register Descriptions
13.2.1 Receive Shift Register
The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into RSR
in the order received, LSB (bit 0) first. In this way the SCI converts received data to parallel form.
When one byte has been received, it is automatically transferred to the receive data register
(RDR). The CPU cannot read or write to RSR directly.
Bit: 7
6
5
4
3
2
1
0
Bit name:
R/W: —
—
—
—
—
—
—
—
13.2.2 Receive Data Register
The receive data register (RDR) stores serial receive data. The SCI completes the reception of one
byte of serial data by moving the received data from the receive shift register (RSR) into RDR for
storage. RSR is then ready to receive the next data. This double buffering allows the SCI to
receive data continuously.
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