HD6417034 Datasheet, PDF (568/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table 20.20 Bus Timing (2) (cont)
Conditions: V_CC = 3.3 V ±0.3V, AV_CC = 3.3 V ±0.3V, AV_CC = V_CC ±0.3V, AV_ref = 3.0 V to
AV_CC, V_SS = AV_SS = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C*
Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C
Item
Symbol Min Max
Unit Figures
AH delay time 1
t_AHD1
AH delay time 2
t_AHD2
Multiplexed address delay time t_MAD
Multiplexed address hold time t_MAH
DACK0, DACK1 delay time 1 t_DACD1
— 40
— 40
— 40
–10 —
— 40
ns 20.63
ns
ns
ns
ns 20.52, 20.53, 20.55–
20.58, 20.63, 20.64
DACK0, DACK1 delay time 2 t_DACD2
DACK0, DACK1 delay time 3*⁵ t_DACD3
— 40
— 40
ns
ns 20.53, 20.57, 20.58,
20.63
DACK0, DACK1 delay time 4 t_DACD4
DACK0, DACK1 delay time 5 t_DACD5
Read delay time 35% duty*¹ t_RDD
50% duty
Data setup time for CAS
CAS setup time for RAS
t_DS
t_CSR
Row address hold time
t_RAH
Write command hold time
t_WCH
Write command
setup time
35% duty*¹ t_WCS
50% duty
— 40
ns 20.55, 20.56
— 40
ns
— t_cyc × 0.35 + 35 ns 20.52, 20.53, 20.55–
—
t_cyc × 0.5 + 35 ns ^{20.59, 20.63}
0*³ —
ns 20.55, 20.57
10 —
ns 20.60–20.62
10 —
ns 20.55, 20.57
15 —
ns
0
—
ns 20.55
0
—
ns
Access time from CAS
precharge*⁴
t_ACP
t_cyc —
−20
ns 20.56
Notes: *1 When frequency is 10 MHz or more.
*2 n is the number of wait cycles.
*3 –5ns for parity output of DRAM long-pitch access.
*4 If the access time is satisfied, t_RDS need not be satisfied.
*5 In the relationship between t_CASD2 and t_CASD3 for t_DACD3, the pair of Min-Max is not
exist in the logical structure.
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