HD6417034 Datasheet, PDF (121/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

6.2.2 Break Address Mask Register (BAMR)
The two break address mask registers—break address mask register H (BAMRH) and break
address mask register L (BARML)—together form a single group. Both are 16-bit read/write
registers. BAMRH determines which of the bits in the break address set in BARH are masked.
BAMRL determines which of the bits in the break address set in BARL are masked. A reset
initializes BAMRH and BARML to H'0000. They are not initialized in standby mode.
BAMRH: Break address mask register H.
Bit:
Bit name:
Initial value:
R/W:
15
BAM31
0
R/W
14
BAM30
0
R/W
13
BAM29
0
R/W
12
BAM28
0
R/W
11
BAM27
0
R/W
10
BAM26
0
R/W
9
BAM25
0
R/W
8
BAM24
0
R/W
Bit:
Bit name:
Initial value:
R/W:
7
BAM23
0
R/W
6
BAM22
0
R/W
5
BAM21
0
R/W
4
BAM20
0
R/W
3
BAM19
0
R/W
2
BAM18
0
R/W
1
BAM17
0
R/W
0
BAM16
0
R/W
• BAMRH bits 15–0 (Break Address Mask 31–16 (BAM31–BAM16)): BAM31–BAM16
specify whether bits BA31–BA16 of the break address set in BARH are masked or not.
BAMRL: Break address mask register L.
Bit:
Bit name:
Initial value:
R/W:
15
BAM15
0
R/W
14
BAM14
0
R/W
13
BAM13
0
R/W
12
BAM12
0
R/W
11
BAM11
0
R/W
10
BAM10
0
R/W
9
BAM9
0
R/W
8
BAM8
0
R/W
Bit:
Bit name:
Initial value:
R/W:
7
BAM7
0
R/W
6
BAM6
0
R/W
5
BAM5
0
R/W
4
BAM4
0
R/W
3
BAM3
0
R/W
2
BAM2
0
R/W
1
BAM1
0
R/W
0
BAM0
0
R/W
• BAMRL bits 15–0 (Break Address Mask 15–0 (BAM15–BAM0)): BAM15–BAM0 specify
whether bits BA15–BA0 of the break address set in BARH are masked or not.
Bits 15–0: BAMn
0
1
n = 31–0
Description
Break address bit BAn is included in the break condition (Initial value)
Break address bit BAn is not included in the break condition
85