HD6417034 Datasheet, PDF (686/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table B.2 Pin States in Address Space Accesses (cont)
DRAM Space
16-Bit Space
2-CAS System
2-WE System
Pin Name
8-Bit Upper
Space Byte
Lower
Byte
Word
Upper
Byte
Lower
Byte
Word
CS7–CS2,
CS0
High High
High
High
High
High
High
CS1
Low
—
—
—
Low
Low
Low
RAS
RAS RAS
RAS
RAS
RAS
RAS
RAS
CASH
High CASH
High
CASH High
High
High
CASL
CAS High
CASL
CASL
CASL
CASL CASL
AH
Low
Low
Low
Low
Low
Low
Low
RD
R Low
Low
Low
Low
Low
Low
Low
W High High
High
High
High
High
High
WRH
R High High
High
High
High
High
High
W High High
High
High
Low
High
Low
WRL
R High High
High
High
High
High
High
W Low
Low
Low
Low
High
Low
Low
A0
A0
A0
A0
A0
A0
A0
A0
A21–A1
Address Address Address Address Address Address Address
AD15–AD8
High-Z Data
High-Z Data
Data
High-Z Data
AD7–AD0
Data High-Z Data
Data
High-Z Data
Data
DPH
High-Z Parity
High-Z Parity Parity
High-Z Parity
DPL
Parity High-Z Parity
Parity High-Z Parity
Parity
R: Read
W: Write
—: The CS1 pin is used as the CASH signal output pin.
RAS: When a row address is output from A21–A0, an address strobe signal is output.
CAS: When a column address is output from A21–A0, an address strobe signal is output.
CASH: When a column address is output from A21–A0 during an upper byte access, an address
strobe signal is output.
CASL: When a column address is output from A21–A0 during a lower byte access, an address
strobe signal is output.
Parity: When a DRAM space parity check is selected with the parity check enable bits
(PCHK1,PCHK0) in the parity control register (PCR), this pin is used as the parity pin.
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