HD6417034 Datasheet, PDF (653/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

A.2.49 Refresh Timer Constant Register (RTCOR)
BSC
• Start Address: H'5FFFFB2
• Bus Width: 8/16/32 (read), 16 (write)
Register Overview:
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
Bit: 7
6
5
4
3
2
1
0
Bit name:
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table A.50 RTCOR Bit Functions
Bit
Bit Name
7–0
(Compare match cycle)
Description
Set with compare match cycle
A.2.50 Timer Control/Status Register (TCSR)
• Start Address: H'5FFFFB8
• Bus Width: 8 (read), 16 (write)
Register Overview:
Bit: 7
6
5
4
Bit name: OVF WT/IT TME
—
Initial value: 0
0
0
1
R/W: R/(W)* R/W R/W
—
Note: * Only 0 can be written, to clear the flag.
WDT
3
2
1
0
—
CKS2 CKS1 CKS0
1
0
0
0
—
R/W R/W R/W
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