HD6417034 Datasheet, PDF (396/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Bit 7: TDRE
0
1
Description
TDR contains valid transmit data
TDRE is cleared to 0 when:
• Software reads TDRE after it has been set to 1, then writes 0 in TDRE
• The DMAC writes data in TDR
TDR does not contain valid transmit data
(Initial value)
TDRE is set to 1 when:
• The chip is reset or enters standby mode
• The TE bit in the serial control register (SCR) is cleared to 0
• TDR contents are loaded into TSR, so new data can be written in TDR
• Bit 6 (Receive Data Register Full (RDRF)): RDRF indicates that RDR contains received data.
Bit 6: RDRF Description
0
RDR does not contain valid received data
(Initial value)
RDRF is cleared to 0 when:
• The chip is reset or enters standby mode
• Software reads RDRF after it has been set to 1, then writes 0 in RDRF
• The DMAC reads data from RDR
1
RDR contains valid received data.
RDRF is set to 1 when serial data is received normally and transferred from
RSR to RDR.
Note:
RDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit
to 0 in the serial control register. They retain their previous contents. If RDRF is still set to 1
when reception of the next data ends, an overrun error (ORER) occurs and the received
data is lost.
• Bit 5 (Overrun Error (ORER)): Indicates that data reception ended abnormally due to an
overrun error.
360