HD6417034 Datasheet, PDF (330/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

10.6.5 Contention between TCNT Write and Overflow/Underflow
If an overflow occurs in the T3 state of a TCNT write cycle, writing takes priority over counter
incrementing. OVF is set to 1. The same applies to underflows. The timing is shown in figure
10.62.
TCNT write cycle
T1
T2
T3
CK
Address
Internal
write signal
TCNT
input clock
Overflow
signal
TCNT address
TCNT
OVF
H'FFFF
M
TCNT write data
Figure 10.62 Contention between TCNT Write and Overflow
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