HD6417034 Datasheet, PDF (12/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Section
Page
2.1.2 Control
18
Registers
Figure 2.2 Control
Registers
2.1.4 Initial Values 19
of Registers
Table 2.1 Initial
Values of Registers
3.1 Types of
49
Operating Modes and
Their Selection
Table 3.1 Operating
Mode Selection
8.11.3 Maximum 174
Number of States
from BREQ Input to
Bus Release
Figure 8.47 Bus
Release Procedure
Description
Description amended
Bits I3–I0: Interrupt mask bits.
Description amended
SR
Bits I3–I0 are 1111(H'F), reserved bits are 0, and other
bits are undefined
Note amended
*2 Only modes 0 and 1 are available in the SH7032 and SH7034
ROMless version.
Description amended
t_BRQS
t_BACD1
t_BACD2
Edition
6
6
6
6
9.1.4 Register
179
Configuration
Table 9.2 DMAC
Registers
9.3.4 DMA Transfer 200
Types
10.1.4 Register
230
Configuration
Table 10.3 Register
Configuration
10.4.5 Reset-
268
Synchronized PWM
Mode
Procedure for
Selecting Reset-
Synchronized PWM
Mode (figure 10.31):
*4 added
6
*4 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9
are ignored. For details on the register addresses, see section
8.3.5, Area Descriptions.
Description amended
6
Line 3
⋅⋅⋅ destination or source must be the SCI or A/D converter
(table 9.4). ⋅⋅⋅
*2 description amended
6
*2 Only 0 can be written to clear flags.
Description amended
6
4. Set bits CMD1 and CMD0 in TFCR to select reset-synchronized
PWM mode. TIOCA3, TIOCB3, TIOCA4, TIOCB4, TOCXA4, and
TOCXB4 become PWM output pins.