HD6417034 Datasheet, PDF (308/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

4. Reset TCNT4 (to H'0000). Set the non-overlap offset in TCNT3. Do not set TCNT3 and
TCNT4 to the same value.
5. GRA3 is the waveform period register. Set the upper limit of TCNT3–1*. Set the transition
times of the PWM output waveforms in GRB3, GRA4, and GRB4. Set times within the
compare match range of TCNT3 and TCNT4.
T≤X
(X: initial setting of GRB3, GRA4, and GRB4; T: initial setting of TCNT3)
Note: *GRA3 = [cycle count/2] + [count of non-overlaps] - 2cyc=[upper limit of TCNT3]-1
6. Set the STR3 and STR4 bits in TSTR to 1 to start the TCNT3 and TCNT4 counts.
Complementary PWM mode
Stop counting
(1)
Select counter clock
(2)
Select complementary
PWM mode
(3)
Set TCNT
(4)
Set general registers
(5)
Start counting
(6)
Complementary PWM mode
Note: To re-establish complementary PWM mode after it has been aborted, start settings from
step 1.
Figure 10.33 Procedure for Selecting Complementary PWM Mode
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