HD6417034 Datasheet, PDF (66/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table 2.9 Instruction Formats (cont)
Instruction Format
d format
15
0
xxxx xxxx dddd dddd
d12 format
15
xxxx dddd
dddd
0
dddd
nd8 format
15
xxxx nnnn
dddd
0
dddd
i format
Source Operand
dddddddd: GBR
indirect with
displacement
Destination
Operand
R0 (Register
direct)
Example
MOV.L
@(disp,GBR),R0
R0 (Register direct) dddddddd: GBR
indirect with
displacement
dddddddd: PC
relative with
displacement
R0 (Register
direct)
dddddddd: PC
—
relative
dddddddddddd: —
PC relative
MOV.L
R0,@(disp,GBR)
MOVA
@(disp,PC),R0
BF
label
BRA label
(label = disp + PC)
dddddddd: PC
relative with
displacement
nnnn: Register
direct
MOV.L
@(disp,PC),Rn
iiiiiiii:
Immediate
Indexed GBR
indirect
AND.B
#imm,@(R0,GBR)
15
0
xxxx xxxx i i i i i i i i
iiiiiiii:
Immediate
R0 (Register
direct)
AND #imm,R0
ni format
15
0
xxxx nnnn i i i i i i i i
iiiiiiii:
Immediate
iiiiiiii:
Immediate
—
nnnn: Register
direct
TRAPA #imm
ADD #imm,Rn
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
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