HD6417034 Datasheet, PDF (25/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

5.3.2 Interrupt Control Register (ICR) .......................................................................... 75
5.4 Interrupt Operation ............................................................................................................ 76
5.4.1 Interrupt Sequence................................................................................................ 76
5.4.2 Stack after Interrupt Exception Handling............................................................. 78
5.5 Interrupt Response Time.................................................................................................... 79
5.6 Usage Notes ....................................................................................................................... 80
Section 6 User Break Controller (UBC) ..................................................................... 81
6.1 Overview............................................................................................................................ 81
6.1.1 Features ................................................................................................................ 81
6.1.2 Block Diagram...................................................................................................... 82
6.1.3 Register Configuration ......................................................................................... 83
6.2 Register Descriptions......................................................................................................... 84
6.2.1 Break Address Registers (BAR) .......................................................................... 84
6.2.2 Break Address Mask Register (BAMR)............................................................... 85
6.2.3 Break Bus Cycle Register (BBR) ......................................................................... 86
6.3 Operation ........................................................................................................................... 88
6.3.1 Flow of User Break Operation ............................................................................. 88
6.3.2 Break on Instruction Fetch Cycles to On-Chip Memory...................................... 90
6.3.3 Program Counter (PC) Value Saved in User Break Interrupt Exception
Processing............................................................................................................. 90
6.4 Setting User Break Conditions .......................................................................................... 91
6.5 Notes.................................................................................................................................. 92
6.5.1 On-Chip Memory Instruction Fetch ..................................................................... 92
6.5.2 Instruction Fetch at Branches ............................................................................... 92
6.5.3 Instruction Fetch Break ........................................................................................ 93
Section 7 Clock Pulse Generator (CPG)..................................................................... 95
7.1 Overview............................................................................................................................ 95
7.2 Clock Source...................................................................................................................... 95
7.2.1 Connecting a Crystal Resonator ........................................................................... 95
7.2.2 External Clock Input ............................................................................................ 97
7.3 Usage Notes ....................................................................................................................... 98
Section 8 Bus State Controller (BSC) ......................................................................... 101
8.1 Overview............................................................................................................................ 101
8.1.1 Features ................................................................................................................ 101
8.1.2 Block Diagram...................................................................................................... 102
8.1.3 Pin Configuration ................................................................................................. 103
8.1.4 Register Configuration ......................................................................................... 104
8.1.5 Overview of Areas................................................................................................ 105
8.2 Register Descriptions......................................................................................................... 107
8.2.1 Bus Control Register (BCR) ................................................................................ 107
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