|
HD6417034 Datasheet, PDF (76/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034 | |||
|
◁ |
Table 2.17 System Control Instructions
Instruction
Instruction Code
Operation
Execution
Cycles
CLRT
0000000000001000 0 â T
1
CLRMAC
0000000000101000 0 â MACH, MACL
1
LDC Rm,SR
0100mmmm00001110 Rm â SR
1
LDC Rm,GBR
0100mmmm00011110 Rm â GBR
1
LDC Rm,VBR
0100mmmm00101110 Rm â VBR
1
LDC.L @Rm+,SR 0100mmmm00000111 (Rm) â SR, Rm + 4 â Rm 3
LDC.L @Rm+,GBR 0100mmmm00010111 (Rm) â GBR, Rm + 4 â Rm 3
LDC.L @Rm+,VBR 0100mmmm00100111 (Rm) â VBR, Rm + 4 â Rm 3
LDS Rm,MACH 0100mmmm00001010 Rm â MACH
1
LDS Rm,MACL 0100mmmm00011010 Rm â MACL
1
LDS Rm,PR
0100mmmm00101010 Rm â PR
1
LDS.L @Rm+,MACH 0100mmmm00000110 (Rm) â MACH, Rm + 4 â 1
Rm
LDS.L @Rm+,MACL 0100mmmm00010110 (Rm) â MACL, Rm + 4 â
1
Rm
LDS.L @Rm+,PR 0100mmmm00100110 (Rm) â PR, Rm + 4 â Rm 1
NOP
0000000000001001 No operation
1
RTE
0000000000101011 Delayed branch, stack area â 4
PC/SR
SETT
0000000000011000 1 â T
1
SLEEP
0000000000011011 Sleep
3*
STC SR,Rn
0000nnnn00000010 SR â Rn
1
STC GBR,Rn
0000nnnn00010010 GBR â Rn
1
STC VBR,Rn
0000nnnn00100010 VBR â Rn
1
STC.L SR,@âRn 0100nnnn00000011 Rnâ4 â Rn, SR â (Rn)
2
STC.L GBR,@âRn 0100nnnn00010011 Rnâ4 â Rn, GBR â (Rn)
2
STC.L VBR,@âRn 0100nnnn00100011 Rnâ4 â Rn, VBR â (Rn)
2
STS MACH,Rn 0000nnnn00001010 MACH â Rn
1
Note: * The number of execution states before the chip enters the sleep state.
T Bit
0
â
LSB
â
â
LSB
â
â
â
â
â
â
â
â
â
â
1
â
â
â
â
â
â
â
â
40
|
▷ |