HD6417034 Datasheet, PDF (28/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

10.2.9 Timer Control Register (TCR) ............................................................................. 242
10.2.10 Timer I/O Control Register (TIOR) ..................................................................... 244
10.2.11 Timer Status Register (TSR) ................................................................................ 246
10.2.12 Timer Interrupt Enable Register (TIER) .............................................................. 247
10.3 CPU Interface .................................................................................................................... 249
10.3.1 16-Bit Accessible Registers.................................................................................. 249
10.3.2 8-Bit Accessible Registers.................................................................................... 251
10.4 Operation ........................................................................................................................... 252
10.4.1 Overview .............................................................................................................. 252
10.4.2 Basic Functions .................................................................................................... 253
10.4.3 Synchronizing Mode ............................................................................................ 262
10.4.4 PWM Mode .......................................................................................................... 264
10.4.5 Reset-Synchronized PWM Mode ......................................................................... 268
10.4.6 Complementary PWM Mode ............................................................................... 271
10.4.7 Phase Counting Mode .......................................................................................... 278
10.4.8 Buffer Mode ......................................................................................................... 280
10.4.9 ITU Output Timing .............................................................................................. 285
10.5 Interrupts............................................................................................................................ 286
10.5.1 Timing of Setting Status Flags ............................................................................. 286
10.5.2 Status Flag Clear Timing...................................................................................... 288
10.5.3 Interrupt Sources and DMAC Activation............................................................. 289
10.6 Notes and Precautions........................................................................................................ 290
10.6.1 Contention between TCNT Write and Clear........................................................ 290
10.6.2 Contention between TCNT Word Write and Increment ...................................... 291
10.6.3 Contention between TCNT Byte Write and Increment........................................ 292
10.6.4 Contention between GR Write and Compare Match............................................ 293
10.6.5 Contention between TCNT Write and Overflow/Underflow ............................... 294
10.6.6 Contention between General Register Read and Input Capture ........................... 295
10.6.7 Contention Between Counter Clearing by Input Capture and
Counter Increment................................................................................................ 296
10.6.8 Contention between General Register Write and Input Capture.......................... 297
10.6.9 Note on Waveform Cycle Setting ........................................................................ 297
10.6.10 Contention between BR Write and Input Capture................................................ 298
10.6.11 Note on Writing in Synchronizing Mode ............................................................. 299
10.6.12 Note on Setting Reset-Synchronized PWM Mode/Complementary
PWM Mode .......................................................................................................... 299
10.6.13 Clearing Complementary PWM Mode ................................................................ 300
10.6.14 Note on Counter Clearing by Input Capture......................................................... 300
10.6.15 ITU Operating Modes .......................................................................................... 301
Section 11 Programmable Timing Pattern Controller (TPC).................................. 309
11.1 Overview............................................................................................................................ 309
11.1.1 Features ................................................................................................................ 309
vi