HD6417034 Datasheet, PDF (223/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

• Bit 2 (Address Error Flag Bit (AE)): AE indicates that an address error has occurred in the
DMAC. When this flag is set to 1, the channel cannot be enabled even if the DE bit in the
DMA channel control register (CHCR) and the DME bit are set to 1. To clear the AE bit, read
1 from it and then write 0. It is initialized to 0 by a reset and in standby mode.
Bit 2: AE
0
1
Description
No DMAC address error
To clear the AE bit, read 1 from it and then write 0
Address error by DMAC
(Initial value)
• Bit 1 (NMI Flag Bit (NMIF)): NMIF indicates that an NMI interrupt has occurred. When this
flag is set to 1, the channel cannot be enabled even if the DE bit in CHCR and the DME bit are
set to 1. To clear the NMIF bit, read 1 from it and then write 0. It is initialized to 0 by a reset
and in standby mode.
Bit 1: NMIF
0
1
Description
No NMI interrupt
To clear the NMIF bit, read 1 from it and then write 0
NMI has occurred
(Initial value)
• Bit 0 (DMA Master Enable Bit (DME)): DME enables or disables DMA transfers on all
channels. A channel becomes enabled for a DMA transfer when the DE bit in each DMA's
CHCR and the DME bit are set to 1. For this to be effective, however, the TE bit of each
CHCR and the NMIF and AE bits must all be 0. When the DME bit is cleared, all channel
DMA transfers are aborted.
Bit 0: DME
0
1
Description
DMA transfers disabled on all channels
DMA transfers enabled on all channels
(Initial value)
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