HD6417034 Datasheet, PDF (311/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

TCNT3
N–1
N
N+1
N
N–1
GRA3
IMFA
Buffer transfer
signal (BR to GR)
GR
TCNT4
N
Set to 1
Flag not set
Buffer transfer performed
Figure 10.36 Overshoot Timing
Buffer transfer
not performed
Underflow Overflow
H' 0001 H' 0000 H' FFFF H' 0000
OVF
Buffer transfer
signal (BR to GR)
GR
Set to 1
Flag not set
Buffer transfer performed
Buffer transfer
not performed
Figure 10.37 Undershoot Timing
The IMFA bit of channel 3 is set to 1 for increment pulses and the OVF bit of channel 4 is set to 1
for underflows only. The buffer register (BR) set for the buffer operation is transferred to GR upon
compare match A3 (when incrementing) or TCNT4 underflow.
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