HD6417034 Datasheet, PDF (656/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table A.53 RSTCSR Bit Functions
Bit Bit Name
Value Description
7
Watchdog timer overflow flag 0
(WOVF)
No TCNT overflow in watchdog timer mode
(Initial value)
Clear Condition: WOVF read, then 0 written in
WOVF
1
TCNT overflow generated in watchdog timer
mode
6
Reset enable (RSTE)
0
No internal reset when TCNT overflows*
(Initial value)
1
Internal reset when TCNT overflows
5
Reset select (RSTS)
0
Power-on reset
(Initial value)
1
Manual reset
Note: * The microprocessor is not reset internally, but TCNT and TCSR within the WDT are reset.
A.2.53 Standby Control Register (SBYCR)
Power-Down State
• Start Address: H'5FFFFBC
• Bus Width: 8/16/32
Register Overview:
Bit: 7
6
5
4
3
2
1
0
Bit name: SBY
HIZ
—
—
—
—
—
—
Initial value: 0
0
0
1
1
1
1
1
R/W: R/W R/W
—
—
—
—
—
—
Table A.54 SBYCR Bit Functions
Bit Bit Name
Value Description
7
Standby (SBY)
0
Shift to sleep mode on execution of SLEEP
instruction
(Initial value)
1
Shift to standby mode on execution of SLEEP
instruction
6
Port high impedance (HIZ) 0
Pin states held in standby mode
(Initial value)
1
Pins change to high impedance in standby mode
620