HD6417034 Datasheet, PDF (148/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table 8.5 Single-Mode DMA Memory Read Cycle States (External Memory Space)
Single-Mode DMA Memory Read Cycle States
(External Memory Space)
Bits 15–8:
WAIT Pin Input
DRW7–DRW0 Signal
Multiplexed
External Memory Space DRAM Space I/O
0
Not sampled during Areas 1, 3–5,7: 1 state, Column address 4 states +
single-mode DMA fixed
memory read cycle* _{Areas 0, 2, 6: 1 state +}
cycle: 1 state, wait states
fixed (short pitch) from WAIT
long wait state
1
Sampled during Areas 1, 3–5, 7: 2 states Column address
single-mode DMA + wait states from WAIT cycle: 2 states +
memory read cycle _{Areas 0, 2, 6: 1 state +}
(Initial value)
long wait state + wait
state from WAIT
wait state from
WAIT (long pitch)
Note: * Sampled in the address/data multiplexed I/O space.
• Bits 7–0 (Single-Mode DMA Memory Write Wait State Control (DWW7–DWW0)): DWW7–
DWW0 determine the number of states in single-mode DMA memory write cycles for each
area and whether or not to sample the WAIT signal. Bits DWW7–DWW0 correspond to areas
7–0, respectively. If a bit is cleared to 0, the WAIT signal is not sampled during the single-
mode DMA memory write cycle for the corresponding area. If it is set to 1, sampling takes
place.
The number of states for areas accesses based on bit settings is the same as indicated for
single-mode DMA memory read cycles. See bits 15–8, Wait State Control During Single-
Mode DMA Memory Transfer (DRW7–DRW0), for details.
Table 8.6 summarizes single-mode DMA memory write cycle state information.
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