HD6417034 Datasheet, PDF (583/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

CK
DREQ0, DREQ1
edge
t_DRQW
Figure 20.66 DREQ0, DREQ1 Input Timing (2)
(5) 16-bit Integrated Timer Pulse Unit Timing
Table 20.22 16-bit Integrated Timer Pulse Unit Timing
Conditions: V_CC = 3.3 V ±0.3V, AV_CC = 3.3 V ±0.3V, AV_CC = V_CC ±0.3V, AV_ref = 3.0 V to
AV_CC, V_SS = AV_SS = 0 V, Ta = –20 to +75°C*
Notes: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C
Item
Output compare delay time
Input capture setup time
Timer clock input setup time
Timer clock pulse width
(single edge)
Timer clock pulse width
(both edges)
Symbol
t_TOCD
t_TICS
t_TCKS
t_TCKWH/L
12.5 MHz
Min Max
—
100
50
—
50
—
1.5 —
t_TCKWL/L 2.5
—
20 MHz
Min Max
—
100
35
—
50
—
1.5 —
Unit
ns
ns
ns
t_cyc
Figure
20.67
20.68
2.5 —
t_cyc
CK
t_TOCD
Output
compare^*1
Input
capture^*2
t_TICS
Notes: *1 TIOCA0–TIOCA4, TIOCB0–TIOCB4, TOCXA4, TOCXB4
*2 TIOCA0–TIOCA4, TIOCB0–TIOCB4
Figure 20.67 ITU Input/Output Timing
547