HD6417034 Datasheet, PDF (206/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Corresponding DRAM conditions: Long-pitch/normal mode
Long-pitch/high-speed page mode
There are no problems regarding operations except for the above conditions.
There are the following four cases (figures 8.38 to 8.41) for the output states of DRAM control
signals (RAS, CAS, and WR) corresponding to RES latch timing. Actual output levels are shown
by solid lines (not by dashed lines).
CK
RES
A0–A21
RAS
CAS
WR
AD0–AD15
RES latch
Tp
timing
Tr
Tc1
Tc2
Manual reset
Row address Column address FFFF
Data output
Figure 8.38 Long-Pitch Mode Write (1)
CK
RES
RES latch
Tp
timing
Manual reset
Tr
Tc1
Tc2
A0–A21
RAS
CAS
Row address FFFF
WR
AD0–AD15
Data output
Figure 8.39 Long-Pitch Mode Write (2)
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