HD6417034 Datasheet, PDF (111/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

5.3.2 Interrupt Control Register (ICR)
ICR is a 16-bit register that sets the input detection mode of external interrupt input pins NMI and
IRQ0–IRQ7, and indicates the input signal level at the NMI pin. A reset initializes ICR but
standby mode does not.
Bit: 15
14
13
12
11
10
9
8
Bit name: NMIL
—
—
—
—
—
—
NMIE
Initial value: *
0
0
0
0
0
0
0
R/W: R
—
—
—
—
—
—
R/W
Bit: 7
6
5
4
3
Bit name: IRQ0S IRQ1S IRQ2S IRQ3S IRQ4S
Initial value: 0
0
0
0
0
R/W: R/W R/W R/W R/W R/W
Note: * When NMI input is high: 1; when NMI input is low: 0
2
IRQ5S
0
R/W
1
IRQ6S
0
R/W
0
IRQ7S
0
R/W
• Bit 15 (NMI input level (NMIL)): NMIL sets the level of the signal input at the NMI pin.
NMIL cannot be modified. The NMI input level can be read to determine the NMI pin level.
Bit 15: NMIL
0
1
Description
NMI input level is low
NMI input level is high
• Bits 14–9 (Reserved): These bits are always read as 0. The write value should always be 0.
• Bit 8 (NMI Edge Select (NMIE)): NMIE selects whether the falling or rising edge of the
interrupt request signal at the NMI pin is sensed.
Bit 8: NMIE
0
1
Description
Interrupt is requested on falling edge of NMI input
Interrupt is requested on rising edge of NMI input
(Initial value)
• Bits 7–0 (IRQ0–IRQ7 Sense Select (IRQ0S–IRQ7S)): IRQ0–IRQ7 select whether the falling
edge or low level of the IRQ inputs is sensed at pins IRQ0–IRQ7.
Bits 7–0: IRQ0S–IRQ7S
0
1
Description
Interrupt is requested when IRQ input is low
Interrupt is requested on falling edge of IRQ input
(Initial value)
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