HD6417034 Datasheet, PDF (122/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

6.2.3 Break Bus Cycle Register (BBR)
The break bus cycle register (BBR) is a 16-bit read/write register that selects the following four
break conditions:
• CPU cycle or DMA cycle
• Instruction fetch or data access
• Read or write
• Operand size (byte, word, longword).
A reset initializes BBR to H'0000. It is not initialized in standby mode.
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
Bit: 7
6
5
4
3
2
1
0
Bit name: CD1 CD0 ID1
ID0 RW1 RW0 SZ1 SZ0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Bits 15–8 (Reserved): These bits are always read as 0. The write value should always be 0.
• Bits 7 and 6 (CPU Cycle/DMA Cycle Select (CD1 and CD0)): CD1 and CD0 select whether to
break on CPU and/or DMA bus cycles.
Bit 7: CD1
0
1
Bit 6: CD0
0
1
0
1
Description
No break interrupt occurs
Break only on CPU cycles
Break only on DMA cycles
Break on both CPU and DMA cycles
(Initial value)
86