HD6417034 Datasheet, PDF (284/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table 10.10 Timer Interrupt Enable Register (TIER)
Channel
0
1
2
3
4
Abbreviation
TIER0
TIER1
TIER2
TIER3
TIER4
Function
TIER controls interrupt enabling/disabling
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
OVIE IMIEB IMIEA
Initial value: *
1
1
1
1
0
0
0
R/W: —
—
—
—
—
R/W R/W R/W
Note: * Undefined
• Bits 7–3 (Reserved): Bit 7 is read as undefined. Bits 6–3 are always read as 1. The write value
to bit 7 should be 0 or 1. The write value to bits 6–3 should always be 1.
• Bit 2 (Overflow Interrupt Enable (OVIE)): When the TSR overflow flag (OVF) is set to 1,
OVIE enables or disables interrupt requests from OVF.
Bit 2: OVIE
0
1
Description
Disables interrupt requests by OVF
Enables interrupt requests from OVF
(Initial value)
• Bit 1 (Input Capture/Compare Match Interrupt Enable B (IMIEB)): When the IMFB bit in TSR
is set to 1, IMIEB enables or disables interrupt requests by IMFB.
Bit 1: IMIEB
0
1
Description
Disables interrupt requests by IMFB (IMIB)
Enables interrupt requests by IMFB (IMIB)
(Initial value)
• Bit 0 (Input Capture/Compare Match Interrupt Enable A (IMIEA)): When the IMFA bit in
TSR is set to 1, IMIEA enables or disables interrupt requests by IMFA.
Bit 0: IMIEA
0
1
Description
Disables interrupt requests by IMFA (IMIA)
Enables interrupt requests by IMFA (IMIA)
(Initial value)
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