HD6417034 Datasheet, PDF (228/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

When outputting transfer requests from on-chip supporting modules, the appropriate interrupt
enable bits must be set to output the interrupt signals. Note that transfer request signals from on-
chip supporting modules (interrupt request signals) are sent not just to the DMAC but to the CPU
as well. When an on-chip supporting module is specified as the transfer request source, set the
priority level values in the interrupt priority level registers (IPRC–IPRE) of the interrupt controller
(INTC) at or below the levels set in the I3–I0 bits of the CPU's status register (SR) so that the CPU
does not acknowledge the interrupt request signal.
The DMA transfer request signals in table 9.4 are automatically withdrawn when the
corresponding DMA transfer is performed. If cycle steal mode is being used, the DMA transfer
request (interrupt request) will be cleared at the first transfer; if burst mode is being used, it will be
cleared at the last transfer.
9.3.3 Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it selects a
channel according to a predetermined priority order. The three modes (fixed mode, round-robin
mode, and external-pin round-robin mode) are selected by priority bits PR1 and PR0 in the DMA
operation register.
Fixed Mode: In this mode, the priority levels among the channels remain fixed. When the PR1
and PR0 bits are set to 00, the priority order, high to low, is Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1. When
the PR1 and PR0 bits are set to 01, the priority order, high to low, is Ch. 1 > Ch. 3 > Ch. 2 > Ch. 0.
Round-Robin Mode: Each time one word or byte is transferred on one channel, the priority order
is rotated. The channel on which the transfer just finished rotates to the bottom of the priority
order. When necessary, the priority order of channels other than the one that just finished the
transfer can also be shifted to keep the relationship between the channels from changing (figure
9.3). The priority order immediately after a reset is channel 0 > channel 3 > channel 2 > channel 1.
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