HD6417034 Datasheet, PDF (14/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Section
Page
12.2.2 Timer
338
Control/Status
Register (TCSR)
13.2.6 Serial Control 359
Register
Description
Note added
Note: * Only 0 can be written, to clear the flag.
Initial value added
Internal clock, SCK pin used for input pin (input signal
is ignored) or output pin (output level is undefined)*²
(Initial value)
Internal clock, SCK pin used for serial clock output*²
(Initial value)
Edition
6
6
13.2.8 Bit Rate
367
Register (BRR)
Table 13.3 Bit Rates
and BRR Settings in
Asynchronous Mode
Table 13.4 Bit 368
Rates and BRR
Settings in
Synchronous Mode
15.2 Register
427
Configuration
Table 15.2 Pin
Function Controller
Registers
16.2.1 Register
442
Configuration
Table 16.1 Port A
Register
16.3.1 Register
443
Configuration
Table 16.3 Port B
Register
16.4.1 Register
445
Configuration
Table 16.5 Port C
Register
Note added
6
Note: Settings with an error of 1% or less are recommended.
Note deleted
6
Note added
6
Name
Abbreviation R/W Initial Value Address* Access Size
Port A I/O register
PAIOR
R/W H'0000
H'5FFFFC4 8, 16, 32
Port A control register 1 PACR1
R/W H'3302
H'5FFFFC8 8, 16, 32
Port A control register 2 PACR2
R/W H'FF95
H'5FFFFCA 8, 16, 32
Port B I/O register
PBIOR
R/W H'0000
H'5FFFFC6 8, 16, 32
Port B control register 1 PBCR1
R/W H'0000
H'5FFFFCC 8, 16, 32
Port B control register 2 PBCR2
R/W H'0000
H'5FFFFCE 8, 16, 32
Column address strobe CASCR
pin control register
R/W H'5FFF
H'5FFFFEE 8, 16, 32
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
Note added
6
Name
Abbreviation R/W Initial Value Address*
Access Size
Port A data register PADR
R/W H'0000
H'5FFFFC0 8, 16, 32
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
Note added
6
Name
Abbreviation R/W Initial Value Address*
Access Size
Port B data register PBDR
R/W H'0000
H'5FFFFC2 8, 16, 32
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
Note added
6
Name
Abbreviation R/W Initial Value Address*
Access Size
Port C data register PCDR
R/W —
H'5FFFFD0 8, 16, 32
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.