HD6417034 Datasheet, PDF (355/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

• Bits 7–0 (Next Data Enable 15–8 (NDER15–NDER8)): NDER15–NDER8 select
enabling/disabling for TPC output groups 3 and 2 (TP15–TP8) in bit units.
Bit 7–0:
NDER15–NDER8
0
1
Description
Disables TPC outputs TP15–TP8 (transfer from NDR15–NDR8 to
PB15–PB8 is disabled)
(Initial value)
Enables TPC outputs TP15–TP8 (transfer from NDR15–NDR8 to
PB15–PB8 is enabled)
11.2.7 TPC Output Control Register (TPCR)
TPCR is an eight-bit read/write register that selects output trigger signals for TPC outputs. TPCR
is initialized to H'FF by a reset. It is not initialized in standby mode.
Bit: 7
6
5
4
3
2
1
0
Bit name: G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Bits 7 and 6 (Group 3 Compare Match Select 1 and 0 (G3CMS1 and G3CMS0)): G3CMS1
and G3CMS0 select the compare match that triggers TPC output group 3 (TP15–TP12).
Bit 7: G3CMS1 Bit 6: G3CMS0 Description
0
0
TPC output group 3 (TP15–TP12) output is triggered by
compare match in ITU channel 0
1
TPC output group 3 (TP15–TP12) output is triggered by
compare match in ITU channel 1
1
0
TPC output group 3 (TP15–TP12) output is triggered by
compare match in ITU channel 2
1
TPC output group 3 (TP15–TP12) output is triggered by
compare match in ITU channel 3
(Initial value)
319