HD6417034 Datasheet, PDF (341/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table 10.21 ITU Operating Modes (Channel 3) (cont)
Register Setting
TSNC
TMDR
TFCR
TOCR
TIOR3
TCR3
Reset
Output
Operating
Comp Sync
Level
Mode
Sync MDF FDIR PWM PWM PWM Buffer Select IOA
IOB
Clear Clock
Select Select
Comple- √*²
—— —
CMD1 CMD1 √
√
—
—
mentary
=1 =1
PWM mode
CMD0 CMD0
=0 =0
CCLR1 √*⁴
=0
CCLR0
=0
Reset
√
—— —
CMD1 CMD1 √
√
—
—
synchron-
=1 =1
ized PWM
CMD0 CMD0
mode
=1 =1
CCLR1 √
=0
CCLR0
=1
Buffer
√
—— √
√
√
BFA3 = —
√
√
(BRA)
1,
others:
don’t
care
√
√
Buffer
√
—— √
√
√
BFB3 = —
√
√
(BRB)
1,
others:
don’t
care
√
√
√: Settable, —: Setting does not affect current mode
Notes: *1 In PWM mode, the input capture function cannot be used. When compare match A and
compare match B occur simultaneously, the compare match signal is inhibited.
*2 When set for complementary PWM mode, do not simultaneously set channel 3 and
channel 4 to function synchronously.
*3 Counter clearing by input capture A cannot be used when reset-synchronized PWM
mode is set.
*4 Clock selection when complementary PWM mode is set should be the same for
channels 3 and 4.
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