HD6417034 Datasheet, PDF (395/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Bit 1: Bit 0:
CKE1 CKE0 Description*¹
0
0
Asynchronous mode Internal clock, SCK pin used for input pin (input signal
is ignored) or output pin (output level is undefined)*²
(Initial value)
Synchronous mode
Internal clock, SCK pin used for serial clock output*²
(Initial value)
0
1
Asynchronous mode Internal clock, SCK pin used for clock output*³
Synchronous mode
Internal clock, SCK pin used for serial clock output
1
0
Asynchronous mode External clock, SCK pin used for clock input*⁴
Synchronous mode
External clock, SCK pin used for serial clock input
1
1
Asynchronous mode External clock, SCK pin used for clock input*⁴
Synchronous mode
External clock, SCK pin used for serial clock input
Notes: *1 The SCK pin is multiplexed with other functions. Set the pin function controller (PFC) to
select the SCK function and SCK input/output for the SCK pin.
*2 Initial value
*3 The output clock frequency is the same as the bit rate.
*4 The input clock frequency is 16 times the bit rate.
13.2.7 Serial Status Register
The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status
flags that indicate the SCI operating status.
The CPU can always read and write to SSR, but cannot write 1 in the status flags (TDRE, RDRF,
ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after
being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. SSR is
initialized to H'84 by a reset and in standby mode.
Bit: 7
6
5
Bit name: TDRE RDRF ORER
Initial value: 1
0
0
R/W: R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written, to clear the flag.
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
• Bit 7 (Transmit Data Register Empty (TDRE)): TDRE indicates that the SCI has loaded
transmit data from TDR into TSR and new serial transmit data can be written in TDR.
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