HD6417034 Datasheet, PDF (244/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

T1 Tw T2 T1 Tw T2
CK
DREQ
Bus cycle
CPU CPU CPU DMAC (R) DMAC (W) CPU CPU
DACK
DMAC (R): DMAC read cycle
DMAC (W): DMAC write cycle
Figure 9.18 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = 2 States + 1 Wait State)
Tp Tr Tc Tc
Tp Tr Tc Tc
CK
DREQ
Bus cycle _{CPU CPU CPU}
DMAC
CPU
DMAC
CPU
DACK
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will
be executed because the sampling is performed at the second state of the DMAC cycle.
Figure 9.19 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = DRAM Bus Cycle
(Long Pitch Normal Mode))
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