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HD6417034 Datasheet, PDF (38/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034 | |||
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Table 1.1 Features of the SH7032 and SH7034 Microcomputers
Feature
CPU
Operating modes
Description
Original Hitachi architecture
32-bit internal data paths
General-register machine:
⢠Sixteen 32-bit general registers
⢠Three 32-bit control registers
⢠Four 32-bit system registers
RISC-type instruction set:
⢠Instruction length: 16-bit fixed length for improved code efficiency
⢠Load-store architecture (basic arithmetic and logic operations are
executed between registers)
⢠Delayed unconditional branch instructions reduce pipeline disruption
⢠Instruction set optimized for C language
Instruction execution time: one instruction/cycle (50 ns/instruction at 20-
MHz operation)
Address space: 4 Gbytes available in the architecture
On-chip multiplier: multiplication operations (16 bits à 16 bits â 32 bits)
executed in 1â3 cycles, and multiplication/accumulation operations (16
bits à 16 bits + 42 bits â 42 bits) executed in 2â3 cycles
Five-stage pipeline
Operating modes:
⢠On-chip ROMless mode
⢠On-chip ROM mode (SH7034 only)
Processing states:
⢠Power-on reset state
⢠Manual reset state
⢠Exception handling state
⢠Program execution state
⢠Power-down state
⢠Bus-released state
Power-down states:
⢠Sleep mode
⢠Software standby mode
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