HD6417034 Datasheet, PDF (151/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
• Bit 15 (Dual-CAS or Dual-WE Select Bit (CW2)): When accessing a 16-bit bus width space,
CW2 selects the dual-CAS or the dual-WE method. When cleared to 0, the CASH, CASL, and
WRL signals are valid ; when set to 1, the CASL, WRH, and WRL signals are valid. When
accessing an 8-bit space, only CASL and WRL signals are valid, regardless of the CW2
setting.
Bit 15L: CW2
0
1
Description
Dual-CAS: CASH, CASL, and WRL signals are valid
Dual-WE: CASL, WRH, and WRL signals are valid
(Initial value)
• Bit 14 (RAS Down (RASD)): When DRAM access pauses, RASD determines whether to keep
RAS low while waiting for the next DRAM access (RAS down mode) or return it to high
(RAS up mode). When cleared to 0, the RAS signal returns to high; when set to 1, it stays low.
Bit 14: RASD
0
1
Description
RAS up mode: Return RAS signal to high and wait for the next DRAM
access
(Initial value)
RAS down mode: Keep RAS signal low and wait for the next DRAM
access
• Bit 13 (RAS Precharge Cycle Count (TPC)): TPC selects whether the RAS signal precharge
cycle (TP) will be 1 state or 2. When TPC is cleared to 0, a 1-state precharge cycle is inserted;
when 1 is set, a 2-state precharge cycle is inserted.
Bit 13: TPC
0
1
Description
1-state precharge cycle inserted
2-state precharge cycle inserted
(Initial value)
• Bit 12 (Burst Operation Enable (BE)): BE selects whether or not to perform burst operation, a
high-speed page mode. When burst operation is not selected (0), the row address is not
compared but instead is transferred to the DRAM every time and full access is performed.
When burst operation is selected (1), row addresses are compared and burst operation with the
same row address as previously is performed (in this access, no row address is output and the
column address and CAS signal alone are output) (high-speed page mode).
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