HD6417034 Datasheet, PDF (643/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

A.2.41 Wait State Control Register 1 (WCR1)
• Start Address: H'5FFFFA2
• Bus Width: 8/16/32
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
15
RW7
1
R/W
14
RW6
1
R/W
13
RW5
1
R/W
12
RW4
1
R/W
11
RW3
1
R/W
10
RW2
1
R/W
9
RW1
1
R/W
BSC
8
RW0
1
R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
—
WW1 —
Initial value: 1
1
1
1
1
1
1
1
R/W: —
—
—
—
—
—
R/W*
—
Note: * Only write 0 in the WW1 bit when area 1 is DRAM space. When it is external memory
space, do not write 0.
Table A.42 WCR Bit Functions
Number of read cycles
Bit Bit Name
WAIT
Pin
Signal
Value Input
External Space
External
DRAM
Memory Space Space
Internal Space
Multi-
On-Chip
plex On-Chip ROM,
I/O Modules RAM
15–8 Read wait 0
state control
(RW7–RW0)
Not
sampled
during
read
cycle
• Areas 1, 3–5, 7:
fixed at 1 cycle
• Areas 0, 2, 6:
1 cycle + long
wait state
Column Wait Fixed at
address state 3 cycles
cycle: Fixed is 4
at 1 cycle cycles
(short-pitch) plus
WAIT
Fixed at 1
cycle
1
Sampled ^{• Areas 1, 3–5, 7:} Column
during
wait state is 2 address
read
cycle
cycles plus
WAIT
cycle: Wait
state is 2
(Initial
value)
• Areas 0, 2, 6:
1 cycle + long
wait state, or
cycles plus
WAIT (long-
pitch)*
wait state from
WAIT
607