HD6417034 Datasheet, PDF (496/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

19.1.2 Register
Table 19.2 summarizes the register related to the power-down state.
Table 19.2 Standby Control Register (SBYCR)
Name
Abbreviation R/W Initial Value Address* Access size
Standby control register SBYCR
R/W H'1F
H'5FFFFBC 8, 16, 32
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
19.2 Standby Control Register (SBYCR)
The standby control register (SBYCR) is an 8-bit read/write register. It is used to enter standby
mode and also sets the port states in standby mode. SBYCR is initialized to H'1F by a reset.
Bit: 7
6
5
4
3
2
1
0
Bit name: SBY
HIZ
—
—
—
—
—
—
Initial value: 0
0
0
1
1
1
1
1
R/W: R/W R/W
—
—
—
—
—
—
• Bit 7 (Standby (SBY)): SBY enables transition to standby mode. The SBY bit cannot be set to
1 while the timer enable bit (bit TME) in timer control/status register TCSR of the watchdog
timer (WDT) is set to 1. To enter standby mode, clear the TME bit to 0 to halt the WDT and
then set the SBY bit.
SBY
0
1
Description
Executing SLEEP instruction puts the chip into sleep mode
Executing SLEEP instruction puts the chip into standby mode
(Initial value)
• Bit 6 (Port High-Impedance (HIZ)): HIZ selects whether I/O ports remain in their previous
states during standby, or are placed in the high-impedance state when standby mode is entered.
The HIZ bit cannot be set to 1 while the TME bit is set to 1. To place the pins of the I/O ports
in high impedance, clear the TME bit to 0 before setting the HIZ bit.
HIZ
Description
0
Port states are maintained during standby
(Initial value)
1
Ports are placed in the high-impedance state in standby
• Bits 5–0 (Reserved): Bit 5 is a read-only bit that is always read as 0. Only write 0 in bit 5.
Writing to bits 4–0 is disabled. These bits are always read as 1.
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