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HD6417034 Datasheet, PDF (546/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034
CK
tTCKS
tTCKS
TCLKA–
TCLKD
tTCKWL
tTCKWH
Figure 20.37 ITU Clock Input Timing
(6) Programmable Timing Pattern Controller and I/O Port Timing
Table 20.10 Programmable Timing Pattern Controller and I/O Port Timing
Case A: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, AVCC = VCC ±10%, AVref = 3.0 V to AVCC,
VSS = AVSS = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C*
Case B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVCC = VCC ±10%, AVref = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 20 MHz, Ta = –20 to +75°C*
Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C
Item
Port output delay time
Port input hold time
Port input setup time
Symbol
tPWD
tPRH
tPRS
Cases A and B
Min
Max
Unit Figure
—
100
ns 20.38
50
—
ns
50
—
ns
510