HD6417034 Datasheet, PDF (565/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table 20.20 Bus Timing (1) (cont)
Conditions: V_CC = 3.3 V ±0.3V, AV_CC = 3.3 V ±0.3V, AV_CC = V_CC ±0.3V, AV_ref = 3.0 V to
AV_CC, V_SS = AV_SS = 0 V, φ = 20 MHz*¹, Ta = –20 to +75°C*²
Notes: *1 ROMless products
*2 Regular-specification products; for wide-temperature-range products, Ta = –40 to
+85°C
Item
Symbol Min Max
Unit Figures
AH delay time 1
t_AHD1
AH delay time 2
t_AHD2
Multiplexed address delay time t_MAD
Multiplexed address hold time t_MAH
DACK0, DACK1 delay time 1 t_DACD1
— 20
— 20
— 30
0
—
— 23
ns 20.63
ns
ns
ns
ns 20.52, 20.53, 20.55–
20.58, 20.63, 20.64
DACK0, DACK1 delay time 2 t_DACD2
DACK0, DACK1 delay time 3*⁷ t_DACD3
— 23
— 20
ns
ns 20.53, 20.57, 20.58,
20.63
DACK0, DACK1 delay time 4 t_DACD4
DACK0, DACK1 delay time 5 t_DACD5
Read delay time 35% duty*² t_RDD
50% duty
Data setup time for CAS
CAS setup time for RAS
t_DS
t_CSR
Row address hold time
t_RAH
Write command hold time
t_WCH
Write command
setup time
35% duty*² t_WCS
50% duty t_WCS
Access time from
CAS precharge*⁶
t_ACP
— 20
ns
— 20
ns
— t_cyc × 0.35 + 12 ns
— t_cyc × 0.5 + 15 ns
0*⁵ —
ns
10 —
ns
10 —
ns
15 —
ns
0
—
ns
0
—
ns
t_cyc —
ns
−20
20.55, 20.56
20.52, 20.53, 20.55–
20.59, 20.63
20.55, 20.57
20.60–20.62
20.55, 20.57
20.55
20.56
Notes: *1 HBS and LBS signals are 25 ns.
*2 When frequency is 10 MHz or more.
*3 n is the number of wait cycles.
*4 Access time from addresses A0 to A21 is tcyc-25 ns.
*5 –5ns for parity output of DRAM long-pitch access.
*6 It is not necessary to meet the t_RDS specification as long as the access time
specification is met.
*7 In the relationship of t_CASD2 and t_CASD3 with respect to t_DACD3, a Min-Max combination
does not occur because of the logic structure.
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