HD6417034 Datasheet, PDF (18/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Section
20.2.3 AC
Characteristics
(1) Clock Timing
Table 20.18 Clock
Timing
Page
522
Description
12.5 MHz added and description amended
Item
EXTAL input high level
pulse width
EXTAL input low level
pulse width
EXTAL input rise time
EXTAL input fall time
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rise time
Clock fall time
Reset oscillation settling
time
Software standby
oscillation settling time
Symbol
t_EXH
t_EXL
t_EXr
t_EXf
t_cyc
t_CH
t_CL
t_Cr
t_Cf
t_OSC1
t_OSC2
12.5 MHz
Min Max
22
—
22
—
—
10
—
10
80
500
30
—
30
—
—
10
—
10
10
—
10
—
20 MHz
Min Max
15
—
15
—
—
5
—
5
50
250
20
—
20
—
—
5
—
5
10
—
10
—
Edition
6
Unit Figures
ns 20.45
ns
ns
ns
ns 20.45, 20.46
ns 20.46
ns
ns
ns
ms 20.47
ms
(2) Control Signal 524
Timing
Table 20.19 Control
Signal Timing
12.5 MHz added and description amended
6
Item
RES setup time
RES pulse width
NMI reset setup time
NMI reset hold time
NMI setup time
NMI hold time
IRQ0–IRQ7 setup time
(edge detection)
IRQ0–IRQ7 setup time
(level detection)
IRQ0–IRQ7 hold time
IRQOUT output delay
time
Bus request setup time
Bus acknowledge delay
time 1
Bus acknowledge delay
time 2
Bus 3-state delay time
Symbol
t_RESS
t_RESW
t_NMIRS
t_NMIRH
t_NMIS
t_NMIH
t_IRQES
t_IRQLS
t_IRQEH
t_IRQOD
t_BRQS
t_BACD1
t_BACD2
t_BZD
12.5 MHz
Min
Max
320
—
20
—
320
—
320
—
160
—
80
—
160
—
160
—
80
—
—
80
80
—
—
80
—
80
—
80
20 MHz
Min
Max
200
—
20
—
200
—
200
—
100
—
50
—
100
—
Unit
ns
t_cyc
ns
ns
ns
ns
ns
Figure
20.48
20.49
100
—
ns
50
—
ns
—
50
ns 20.50
50
—
ns 20.51
—
50
ns
—
50
ns
—
50
ns
(3) Bus Timing
Table 20.20 Bus
Timing (1)
(3) Bus Timing
Table 20.20 Bus
Timing (2)
528
Description amended
Read data access time 2*⁶ t_ACC2
530 to Newly added
532
t_cyc × (n+2) – —
30*³
6
ns 20.53, 20.54, 20.57–20.59
6