HD6417034 Datasheet, PDF (189/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

The high-level duty of the CAS signal can be selected in short-pitch, high-speed page mode
using the CAS duty bit (CDTY) in DCR. When the CDTY bit is cleared to 0, the high-level
duty is 50% of the T_C state; when CDTY is set to 1, it is 35% of the T_C state.
• Long-pitch, high-speed page mode: When the RW1, WW1, DRW1, and DWW1 bits in WCR1
and WCR2 are set to 1, and the corresponding DRAM access cycle is continuing, the CAS
signal and column address output cycles (2 states) continue as long as the row addresses
continue to match. When the WAIT signal is detected at the low level, the second cycle of the
column address output cycle is repeated as the wait state. Figure 8.26 shows the timing for
long-pitch, high-speed page mode. See sections 20.1.3 (3) and 20.2.3 (3), Bus Timing, for
more information about the timing.
T_p
T_r
T_c1
T_c2
T_c1
T_c2
CK
A21–AD0
RAS
CAS
WR
Read
AD15–AD0
Column address 1 Column address 2
Row address 1
Data 1
Data 2
WR
Write
AD15–AD0
Data 1
Data 2
Figure 8.26 Long-Pitch, High-Speed Page Mode (Read/Write Cycle)
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