HD6417034 Datasheet, PDF (190/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

RAS Down Mode and RAS Up Mode: Sometimes access to another area can occur between
accesses to the DRAM even though burst operation has been selected. Keeping the RAS signal
low while this other access is occurring allows burst operation to continue the next time the same
row of the DRAM is accessed. The RASD bit in DCR selects RAS down mode when set to 1 and
RAS up mode when cleared to 0. In both RAS down mode and RAS up mode, burst operation is
continued while the same row address continues to be accessed, even if the bus master is changed.
• RAS down mode: When the RASD bit in DCR is set to 1, the DRAM access pauses and the
RAS signal is held low throughout the access of the other space while waiting for the next
access to the DRAM area. When the row address for the next DRAM access is the same as the
previous DRAM access, burst operation continues. Figure 8.27 shows the timing of RAS down
mode when external memory space is accessed during burst operation.
The RAS signal can be held low in the DRAM for a limited time; the RAS signal must be
returned to high within the specified limits even when RAS down mode is selected since the
critical low level period is set. In this chip, even when RAS down mode is selected, the RAS
signal automatically reverts to high when the DRAM is refreshed, so the BSC’s refresh control
function can be employed to set a CAS-before-RAS refresh that will keep operation within
specifications. See section 8.5.6, Refresh Control, for details.
CK
A21–
A0
RAS
CAS
WR
AD15–
AD0
DRAM access
External memory
space access _{DRAM access}
T_p
Tr
T_c
T_c
T1
T_c
T_c
Column Column External Column Column
address 1 address 2 memory address 3 address 4
Row address
Data 1
Data 2
External
memory data
Data 3
Data 4
Figure 8.27 RAS Down Mode
154