HD6417034 Datasheet, PDF (100/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

4.7 Stack Status after Exception Handling
Table 4.10 shows the stack after exception handling.
Table 4.10 Stack after Exception Handling
Type
Address
error
Stack Status
Address of
SP instruction Upper 16 bits
after instruc-
tion that has
finished
executing
Lower 16 bits
SR Upper 16 bits
Lower 16 bits
Type
Interrupt
Stack Status
Address of
SP instruction Upper 16 bits
after instruc-
tion that
has finished
executing
Lower 16 bits
SR Upper 16 bits
Lower 16 bits
Trap
instruc-
tion
Address of
SP instruction Upper 16 bits
after TRAPA
instruction
Lower 16 bits
SR Upper 16 bits
Lower 16 bits
Illegal
slot
instruc-
tion
Branch
SP destination Upper 16 bits
address of
delayed
branch
instuction
Lower 16 bits
SR Upper 16 bits
Lower 16 bits
General
illegal
instruc-
tion
SP
Start add-
ress of
illegal
instruction
SR
Upper 16 bits
Lower 16 bits
Upper 16 bits
Lower 16 bits
Note: Stack status is based on a bus width of 16 bits.
64