HD6417034 Datasheet, PDF (275/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

10.2.6 Timer Counters (TCNT)
The ITU has five 16-bit timer counters (TCNT), one for each channel.
Each TCNT is a 16-bit read/write counter that counts by input from a clock source. The clock
source is selected by timer prescaler bits 2–0 (TPSC2–TPSC0) in the timer control register (TCR).
TCNT0 and TCNT 1 are strictly up-counters. Up/down-counting occurs for TCNT2 when phase
counting mode is selected, or for TCNT3 and TCNT 4 when complementary PWM mode is
selected. In other modes, they are up-counters.
TCNT can be cleared to H'0000 by compare match with the corresponding general register A or B
(GRA, GRB) or input capture to GRA or GRB (counter clear function).
When TCNT overflows (changes from H'FFFF to H'0000), the overflow flag (OVF) in the timer
status register (TSR) is set to 1. The OVF of the corresponding channel TSR is also set to 1 when
TCNT underflows (changes from H'0000 to H'FFFF).
TCNT is connected to the CPU by a 16-bit bus, so it can be written or read by either word access
or byte access. TCNT is initialized to H'0000 by a reset and in standby mode.
Table 10.4 Timer Counters (TCNT)
Channel
0
1
2
Abbreviation
TCNT0
TCNT1
TCNT2
3
TCNT3
4
TCNT4
Function
Increment counter
Phase counting mode: Increment/decrement
All others: Increment
Complementary PWM mode: Increment/decrement
All others: Increment
Bit: 15
14
13
12
11
10
9
8
Bit name:
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Bit name:
Initial value:
R/W:
7
6
0
0
R/W R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
239