HD6417034 Datasheet, PDF (441/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Internal
base clock
Receive
data (RxD)
16 clocks
8 clocks
0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5
–7.5 clocks +7.5 clocks
Start bit
D0
D1
Synchronization
sampling
timing
Data
sampling
timing
Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
M = 0.5 – ¹
2N
– (L
–
0.5)F –
D – 0.5
N
(1 + F )
× 100%
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation 2.
Equation 2:
D = 0.5, F = 0
M = (0.5 – 1/(2 × 16)) × 100%
= 46.875% (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20–30%.
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